1. Field of the Invention
The present invention relates to the manufacture of transistors in semiconductor substrates. More particularly, the present invention relates to a method of forming optimized source/drain doping profiles to improve performance in devices having reduced dimensions.
2. Description of the Related Art
Today""s semiconductor devices are continually being pushed to meet stricter demands. As devices using this technology inundate the marketplace, consumers place higher demands on the devices. These demands include smaller, more compact devices with greater functionality.
Semiconductor devices employ various circuitry in a chip to perform user specified functions. As is well known, the circuitry consists of various metallization lines, dielectric layers and other components interconnected throughout the entire chip. The metallization lines and other components are connected to transistors located at a lower level of the semiconductor device. As is well known, the basic transistor has source and drain regions which are separated by a gate. By way of applying different voltages to the gate electrode, the transistor is either said to be ON or OFF.
Although there is a growing demand to scale transistor gate lengths to about 100 nm (i.e., 0.10 micron) and below for more demanding and compact digital circuit applications, such physical dimensions pose certain complications. For example, there is a need to cutoff leakage current in the OFF state, and to produce low resistance or high device current in the ON state. However, for small gate length devices, even in the OFF state, the space-charge region near the drain touches the source in a deeper place where the gate bias cannot control the potential, resulting in leakage current from the source to drain via the space-charge region. This is known as short-channel effect (SCE) which causes degradation in threshold voltage. As can be understood, for a transistor to work as a component of a digital circuit, the capability of switching OFF or the suppression of SCE is of high importance.
FIG. 1 illustrates a conventional transistor structure 22 formed in a substrate 10. The transistor structure 22 is shown having a gate electrode 16 and a gate oxide 18. In an effort to suppress SCE, deep source-drains (DSDs) 12 incorporating heavily doped shallow source-drain extensions (SDE) are formed. As shown, the SDEs are formed near the edges of a gate electrode 16. An additional channel doping called xe2x80x9cpocketxe2x80x9d is also implanted around the SDE regions. To achieve an acceptable OFF state (e.g., leakage current less than 10 nA/xcexcm), pocket doping concentrations in excess of 4xc3x971018 cmxe2x88x923 is required. Such an extreme level of doping concentration in conjunction with high channel concentrations 24 (shown in FIG. 1) of about 1xc3x971018 cmxe2x88x923 used in sub-100 nm transistors (e.g., MOSFETs), causes a very high threshold voltage (Vth) resulting in high ON resistance, thus preventing the operation of the transistor at target supply voltages of about 1V or less. Thus, in the prior art, a trade off is made to reduce leakage currents by implementing high channel concentrations that necessarily require higher threshold voltages to turn ON the transistor.
Yet another problem with the manufacture of sub-100 nm transistors is the susceptibility to punch through. Punch through is generally understood to mean a case in which a dopant annealing process causes the source and drain depletion regions to come together. Since sub-100 nm transistors are pushing the limits on semiconductor manufacturing, transistor shorting or leakage due to punch through is a problem that needs to be addressed.
In view of the foregoing, there is a need for optimized source-drain regions for small transistors (e.g., in the range of 100 nm and below). The optimized source-drain regions should be configured to reduce the exposure of the transistor to leakage currents, and should be configured to reduce channel concentrations just below the gate in order to reduce channel resistance and the magnitude of the applied threshold voltage to successfully and rapidly turn ON the transistor. The optimized source-drain regions should also enable the manufacture of even shorter gate lengths while minimizing the likelihood of leakage currents, punch through, and excessive channel resistance.
Broadly speaking, the present invention fills these needs by providing an optimized transistor structure having dimensions in the range of about 100 nm and below. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for forming transistor source/drain regions in a substrate is disclosed. The source/drain regions have a first polarity. A shallow halo region being of the first polarity and having a first concentration is implanted. A deep halo region also of the first polarity and having a second concentration that is lower than the first concentration is then implanted. The deep halo region is implanted deeper into the substrate than the shallow halo region.
In another embodiment, a transistor structure is disclosed. The transistor structure comprises a substrate having a first polarity. The substrate includes a shallow halo implant being of the first polarity and defined at a first depth within the substrate. The substrate also has a deep halo implant being of the first polarity and defined at a second depth that is greater than the first depth of the shallow halo implant.
In yet another embodiment, a transistor having source/drain regions in a substrate is disclosed. Each source/drain region comprises an extension implant region and a shallow halo implant region defined below the extension implant region. Each source/drain region also comprises a deep halo implant region defined below the shallow halo implant region and a deep implant region defined down to the deep halo implant region.
The many advantages of the present invention should be recognized. The present invention allows designers to design transistors with smaller dimensions. The new transistors avoid the problems of the prior art, namely, of leakage current, punch through and high ON resistance, while at the same time maintaining high threshold voltages as the gate lengths within transistors decrease.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.